Adelaide Research & Scholarship
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https://hdl.handle.net/2440/28360
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| Type: | Conference paper |
| Title: | A parallel architecture for estimating 4th-order cumulants |
| Author: | Lim, J. Lim, C. |
| Citation: | Conference proceedings: IEEE International Symposium on Circuits and Systems / vol. 4, pp. 322-325 |
| Publisher: | IEEE |
| Publisher Place: | CD-ROM |
| Issue Date: | 2001 |
| ISBN: | 0780366859 9780780366855 |
| ISSN: | 0272-9172 |
| Conference Name: | IEEE International Symposium on Circuits and Systems (2001 : Sydney, Australia) |
| Editor: | Skellern, D. Hellestrand, G. |
| Statement of Responsibility: | Lim, J.G. ; Lim, C.C. |
| Abstract: | A novel parallel architecture for estimating computationally intensive 4th-order cumulants is presented. Different from most systolic array implementations, a MIMD array processor is used to efficiently compute the cumulants by exploiting the algorithmic parallelism, reducing operand-fetching operations and by optimising the processing elements' architectural design. It is shown that by breaking the algorithm into a number of separate stages and reorganising all computations in matrix block form, a significant computational speed-up can be obtained, which increases the applicability of cumulant-based algorithms in a real-time system. |
| Description: | © Copyright 2001 IEEE |
| DOI: | 10.1109/ISCAS.2001.922237 |
| Published version: | http://dx.doi.org/10.1109/iscas.2001.922237 |
| Appears in Collections: | Aurora harvest 2 Electrical and Electronic Engineering publications |
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