Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/28445
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Type: | Conference paper |
Title: | Coverage measurement for software application level verification using symbolic trajectory evaluation techniques |
Author: | Cheng, A. Parashkevov, A. Lim, C. |
Citation: | DELTA 2004 : second IEEE International Workshop on Electronic Design, Test and Applications : proceedings:pp.237-242 |
Part of: | Proceedings on the 2nd IEE International Workshop on Electronic Design, Test and Applications 2004 |
Publisher: | IEEE |
Publisher Place: | Los Alamitos, California |
Issue Date: | 2004 |
Series/Report no.: | International Symposium on Electronic Design Test and Applications DELTA |
ISBN: | 0769520812 9780769520810 |
Conference Name: | IEEE International Workshop on Electronic Design, Test and Applications (2nd : 2004 : Perth, Australia) |
Editor: | Osseiran, A. |
Statement of Responsibility: | Adriel Cheng, Atanas Parashkevov, Cheng-Chew Lim |
Abstract: | Design verification of a systems-on-a-chip is a bottleneck for hardware design projects. A new solution is a design verification methodology that applies coverage driven verification at the embedded software application level. This methodology currently lacks an appropriate coverage measurement technique. This paper proposes a new coverage model for the software application level. Using this coverage model, a novel technique to represent and measure coverage is described. This technique uses ideas such as control graph structures and checking algorithms to estimate the completeness of software application verification. |
Description: | Copyright © 2004 IEEE |
DOI: | 10.1109/DELTA.2004.10047 |
Published version: | http://dx.doi.org/10.1109/delta.2004.10047 |
Appears in Collections: | Aurora harvest 6 Electrical and Electronic Engineering publications |
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hdl_28445.pdf | 150.21 kB | Publisher's PDF | View/Open |
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