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https://hdl.handle.net/2440/35215
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Type: | Conference paper |
Title: | Exploiting concurrency in system-on-chip verification |
Author: | Xu, X. Lim, C. |
Citation: | IEEE Asia Pacific Conference on Circuits and Systems, 4-7 Dec, 2006:pp.836-839 |
Publisher: | IEEE |
Publisher Place: | CDROM |
Issue Date: | 2006 |
ISBN: | 1424403871 9781424403875 |
Conference Name: | IEEE Asia Pacific Conference on Circuits and Systems (2006 : Singapore) |
Editor: | Lim, Y. |
Statement of Responsibility: | Xu, Justin; Cheng-Chew Lim |
Abstract: | System-on-chip (SoC) design paradigm makes design verification a more time-consuming task. Therefore, for simulation-based methods, test quality is extremely important. This paper presents a method that increases the test quality by exploiting the concurrency in a system. The main idea is to generalize the elements of concurrency as transfers and then transform the system into a transfer-resource-graph. The graph can be traversed to produce high-quality tests. To further optimize the test quality in terms of concurrency, we are able to generate event-driven test-programs. |
Description: | Copyright © 2006 IEEE |
DOI: | 10.1109/APCCAS.2006.342151 |
Grant ID: | http://purl.org/au-research/grants/arc/LP0454838 |
Published version: | http://dx.doi.org/10.1109/apccas.2006.342151 |
Appears in Collections: | Aurora harvest 6 Electrical and Electronic Engineering publications |
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