Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/64509
Type: | Conference paper |
Title: | Approximate signed binary integer multipliers for arithmetic data value speculation |
Author: | Kelly, D. Phillips, B. Al-Sarawi, S. |
Citation: | Proceedings of the 2009 Conference on Design & Architectures For Signal And Image Processing / M. Mattavelli (ed.): pp.97-104 |
Publisher: | ECSI |
Publisher Place: | online |
Issue Date: | 2009 |
Conference Name: | Conference on Design & Architectures For Signal And Image Processing (2009 : Sophia Antipolis, France) |
Editor: | Marco Mattavelli, |
Statement of Responsibility: | Daniel R. Kelly, Braden J. Phillips and Said Al-Sarawi |
Abstract: | Arithmetic data value speculation increases the throughput of a processor pipeline by speculatively issuing the dependent operations of an arithmetic operation based on the early arrival of an approximate result. Suitable approximate multipliers calculate a product faster than an exact multiplier, with an associated probability that the approximate product is correct. This paper presents the design of a family of signed approximate multipliers for use in a speculative data path. A signed 32x32 bit multiplier synthesised with the TSMC Artisan 180nm SAGE-X™ cell library is found to be 20% faster than a full-adder based tree multiplier, with a probability of error less than 14% for benchmark applications. |
Rights: | Copyright status unknown |
Description (link): | http://www.ecsi.org/resource/approximate-signed-binary-integer-multipliers-arithmetic-data-value-speculation |
Published version: | http://www.ecsi.org/sites/default/files/rs5.1.pdf |
Appears in Collections: | Aurora harvest Electrical and Electronic Engineering publications |
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