Investigations into methods and analysis of computer aided design of VLSI circuits

Abstract

This thesis analyses a range of Computer Aided VLSI design tools that have been developed at the University of Adelaide. The work reviews different IC technologies and summarises some of the overall philosophies behind the development of VLSI CAD tools. In addition, Multi Project Chip processes and iheir relatïonship to various CAD tools is examined and thoughts offered on the merits of full custom IC design as opposed to semi-custom design techniques. The work for this thesis has been completed over a four and a half year period beginning in early 1982, when MPC processes were first introduced to Australia. As a result, the comments made on VLSI design software and MPC processes are strongly associated with the problems experienced with these topics in the Australian environment. An investigation of a mosk level CAD toot set is made and a summary of the tools comprising the complete set, by comparison with some early generation tooìs that originatetl from other universities such as USC Berketey and MIT, is then offered. The work also investigates a symbolic level CAD tool set, the VIVID system, which originated from the Microelectronics Center of North Carolina to run under the UNIX operating system. VIVID was developed for the VMS operating system by ongoing research ai the Universiby of Adelaìde. In addition, other tools that are generally classified as higher level tools than either mask or symbolic level tools are also discussed for the purposes of comparing the directions of tool development. The thesis presents a detailed analysis of the tools discussed by presenting one complete nMOS MPC design experi.nce in detail (including testing of the fabricated product), and provid'ing information on a ,..on,ì de.sign experie¡ce for the purposes of comparison of the layout tools discussed. The results of this work also allow comparison of two different Australian MPC processes using the nMOS technology as both designs discussed were fabricated using different MPC processes- A simila.r account of a detailed design experience using the CMOS technology in conjunction with the symbolic level tools is presented and new Australian CMOS MPC process foreshadowed. This experience, considered with the .urii., mask level design experiences, provides the basis for some final comparitive results to be made between the retative efficiency of desìgning IC's with low level and high level tools. As a result, the work finally presents conclusions regarding the future development of VLSI CA'D tool sets with particular reference being made to Silicon Compilation. The thesis trïes to draw an analogy between levels of VLSI CAD tool sets and levels of languages used to program computers in an effort to indicate possible future directions for development of these tools. In po.ti.rrlur, the thesis examìnes reasonõ why the symbolic level tools may prove to be the first step on the way towards making true Silicon Compilation a reality. Two different IC technologies, nMOS and CMOS, are used to atlow the close analysis and investigation of these tool sets. A number of circuits have been fabricated using the tools and Australian MPC processes and the simulated and tested results of the designs are used to verify the conclusions regarding the tools.