Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/28565
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Type: | Conference paper |
Title: | A software test program generator for verifying system-on-chips |
Author: | Cheng, A. Lim, C. Parashkevov, A. |
Citation: | Proceedings of the Tenth Annual IEEE International High Level Design Validation and Test Workshop : pp. 79-86 |
Publisher: | IEEE |
Publisher Place: | USA |
Issue Date: | 2005 |
Series/Report no.: | IEEE International High Level Design Validation and Test Workshop |
ISBN: | 0780395719 9780780395718 |
ISSN: | 1552-6674 |
Conference Name: | IEEE International High Level Design Validation and Test Workshop (10th : 2005 : Napa Valley, California) |
Editor: | Harris, I. Jones, R. |
Statement of Responsibility: | Cheng, A.; Cheng-Chew Lim; Parashkevov, A. |
Abstract: | Design verification is crucial for successful systems-on-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a technique to test the SoC at the system level using software application based programs. Our software application level verification methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios. |
Description: | © 2005 IEEE. |
DOI: | 10.1109/HLDVT.2005.1568818 |
Published version: | http://dx.doi.org/10.1109/hldvt.2005.1568818 |
Appears in Collections: | Aurora harvest 6 Electrical and Electronic Engineering publications |
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hdl28565.pdf | 382.67 kB | Publisher's PDF | View/Open |
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